Synopsys Design Compiler Tutorial 2021 !full! Official
# Assume external chip paths take 30% of clock cycle set_input_delay 3.0 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 3.0 -clock sys_clk [all_outputs] Use code with caution. Design Environment Constraints
# Define the target silicon technology library set target_library /path/to/foundry/libraries/target_library.db # Define the link library (includes target library and RAM/IP blocks) set link_library * /path/to/foundry/libraries/target_library.db /path/to/ip/ram.db # Define the synthetic library for DesignWare components set synthetic_library dw_foundation.sldb # Combine link and synthetic libraries for complete resolution set link_library [concat $link_library $synthetic_library] # Define where Design Compiler looks for source files set search_path [concat $search_path ./src ./libs /path/to/foundry/libraries] # Define a directory for intermediate work files define_design_lib WORK -path ./WORK Use code with caution. Key Library Definitions: synopsys design compiler tutorial 2021
################################################################### # Synopsys Design Compiler Automation Script ################################################################### # 1. Setup paths and directories file mkdir reports file mkdir outputs # 2. Read Design analyze -format verilog my_alu.v control_unit.v top_module.v elaborate top_module current_design top_module # 3. Link and Check link check_design # 4. Apply Constraints create_clock -name sys_clk -period 10.0 [get_ports clk] set_clock_uncertainty 0.20 [get_clocks sys_clk] set_input_delay 2.5 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 2.5 -clock sys_clk [all_outputs] set_driving_cell -lib_cell BUFX4 [remove_from_collection [all_inputs] [get_ports clk]] set_load 0.2 [all_outputs] # 5. Compile compile_ultra -gate_clock # 6. Generate Reports report_design > reports/design_summary.rpt report_area -hierarchy > reports/area_summary.rpt report_timing -max_paths 5 > reports/timing_worst_paths.rpt report_constraint -all_violators > reports/violations.rpt # 7. Export Outputs change_names -rules verilog -hierarchy write -format verilog -hierarchy -output outputs/top_module_netlist.v write_sdc outputs/top_module.sdc echo "========================================" echo "SYNTHESIS FLOW COMPLETED SUCCESSFULLY!" echo "========================================" exit Use code with caution. Executing the Script via Command Line # Assume external chip paths take 30% of
Design Compiler operates in two primary modes: Wire Load Model (WLM) mode and Topographical mode. Setup paths and directories file mkdir reports file
